Intrinsic ID at Frost & Sullivan Awards Gala – 24 January 2018

Way to go Intrinsic ID team!

Frost & Sullivan Recognizes Intrinsic ID with Technology Leadership Award for IoT Security

Noted for technology utilizing unique, unclonable device identities

SUNNYVALE, Calif. – Oct. 23, 2017 – Intrinsic ID®, the  world’s leading provider of digital authentication technology for Internet of Things security and embedded applications, today announced it has been recognized with the 2017 Frost & Sullivan Technology Leadership Award for Device-Level Digital Authentication Technology for IoT. The recognition stems from Frost & Sullivan’s ongoing analysis of the growth in the Internet of Things market, and the accompanying expectation that digital security companies that can provide device-level digital authentication technology for IoT devices are expected to secure leadership positions in IoT security.

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SmartRG® Joins prpl Foundation in Support of Open-Source Development in the Connected Device Industry

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SmartRG Inc., a leading provider of carrier-grade, open source-based connected home platforms and cloud services, announced today its membership to the prpl Foundation. prpl, the open-source, community-driven, non-profit foundation shaping the next-generation of connected devices, has been steadily gaining members to collectively steer the future of residential broadband.
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prpl Foundation members talk security and virtual platforms at 7th RISC-V workshop

By Art Swift – President, prpl Foundation

Over the past few days, prpl and our member companies Microsemi ( and Imperas ( had the pleasure of attending the sold-out 7th RISC-V workshop held at Western Digital’s conference center in San Jose. Microsemi and Imperas are members of both prpl and the RISC-V foundation. (

For those who don’t know, RISC-V is an open, free instruction set architecture (ISA) developed at the University of California – Berkeley. Support for the new architecture is growing rapidly, as evidenced by the many great presentations from academia and industry, but in certain important areas, RISC-V is still in the early phases of definition, specification, or ecosystem development.


Cesare Garlati, prpl’s chief security strategist and Richard Newell, Microsemi product architect at the 7th RISC-V workshop
Simon Davidmann, CEO of Imperas, during his lightning talk at the 7th RISC-V workshop (photo courtesy of Imperas)








In security for instance, Richard Newell, product architect at Microsemi, is co-chair of a RISC-V task group defining a set of security and cryptographic extensions for the RISC-V ISA. At the workshop, Richard gave two well-received talks. The first, “Security task group update and RISC-V security extension” outlined the current state of the proposed RISC-V security extensions; and the second, “Using Proposed Vector and Crypto Extensions For Fast and Secure Boot,” demonstrated the possibility for some dramatic benefits of these extensions if ratified.

The open and collaborative nature of both the RISC-V and prpl foundations has enabled a hearty exchange of ideas between the groups on security-related industry needs. Richard and his co-chair Joe Xie of NVIDIA recently invited Cesare Garlati, prpl’s chief security strategist, to give a presentation on the prpl security framework to the members of the RISC-V security task group. Cesare was invited back a second time, and we’ve invited Richard to present his RISC-V talk to the prpl virtualization and security working group. We are delighted to work in a friendly collaborative way to make sure that industry best practices for security are adopted across all processor architectures.

Given that many RISC-V based SoCs are now in development, chip simulation is another must-have technology area that the RISC-V ecosystem will need to be successful. It appears that prpl member company Imperas is in “the right place at the right time.” CEO Simon Davidmann took the opportunity at the RISC-V workshop to announce the release of its new RISC-V Processor Developer Suite™ which contains the models and tools necessary to validate and verify the functionality of a RISC-V processor.

As Simon noted in the Imperas press release, “Designing and delivering RISC-V processors is challenging. With the RISC-V Processor Developer Suite, Imperas is providing a solution that accelerates RISC-V development schedules and improves IP quality.”

Congrats to both Microsemi and Imperas for the great showing at the RISC-V workshops! We’re glad to have you participating in both prpl and RISC-V and look forward to the continuing exchange of ideas between the two open source and open standard based foundations!

Recap: Arm TechCon 2017 Hypervisor Panel with prpl and Imperas

A well-attended and lively recent ARM TechCon panel explored the topic “Hypervisors: A Real Trend in Embedded, or Just Hype?”  Moderated by Brian Bailey of Semiconductor Engineering (R), panelists (L to R) were: Cesare Garlati, prpl Foundation, chief security officer; Simon Davidmann, Imperas Software, founder and CEO; Jack Greenbaum, Green Hills Software, director of engineering, advanced products; and Chris Turner, ARM, Director of Emerging Technology & Strategy.

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The panel explored issues around security and functional safety in embedded system development, especially where software touches the hardware. Offering a range of perspectives in the hypervisor ecosystem, panelists addressed changing processor architectures, hardware virtualization extensions and TrustZone, hypervisors, and real time operating systems (RTOSs) as components of the security/safety solution for embedded systems.

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OpenWrt Summit Wrap Up 2017


This year we were delighted to have had yet another successful OpenWrt Summit! It’s wonderful to see participation grow every year, across both community and industry. We especially thank our gracious local host, Turris Omnia. We also thank our Platinum sponsors: prpl, Inteno, Sentinel, and Intel; and Gold sponsors: CZ.NIC, Sartura, and Technicolor. Without their generous support, use of a comfortable conference center in the beautiful city of Prague would not have been possible.
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